/*******************************************************************************
COPYRIGHT 2015   : ATECH
Project          : 
Source File Name : drv_canCfg.h
Group            : SoftWare Team
Author           : 
Date First Issued: 06/08/2015
********************************Documentation**********************************
Purpose -  This file is freescale mc9s12XHY family CAN driver header file
********************************RevisionHistory********************************
_______________________________________________________________________________
Date : MM/DD/YY    Release        Changes Description                  Author
Date : 06/08/2015    1.0                                                 
   
******************************************************************************/ 

#ifndef	drv_canCfg_h
#define	drv_canCfg_h


/* #include */
#include "system.h"
#include "msg_canType.h"

/*****************************************************************************/
/**
* Function Name: INIT_BRP,INIT_TS
* Description:  
*
* 0x01 sync jump - 1 Tq clocks, prescalar=0x3A, Tseg2=4, Tseg1=11, 1 sample per bit
* Baud rate prescaler: for 16 quantas and 75% sample point
*
* Param:   
*          ...
* Author:  
******************************************************************************/
#define CAN_INIT_BRP_125k_8MHz      (UINT8)0x03   
#define CAN_INIT_TS_125k_8MHz       (UINT8)0x3A     

#define CAN_INIT_BRP_250k_8MHz      (UINT8)0x01    
#define CAN_INIT_TS_250k_8MHz       (UINT8)0x3A    

#define CAN_INIT_BRP_500k_8MHz      (UINT8)0x00    
#define CAN_INIT_TS_500k_8MHz       (UINT8)0x3A    

#define CAN_INIT_BRP_125k_16MHz     (UINT8)0x07   
#define CAN_INIT_TS_125k_16MHz      (UINT8)0x3A    

#define CAN_INIT_BRP_250k_16MHz     (UINT8)0x03    
#define CAN_INIT_TS_250k_16MHz      (UINT8)0x3A    

#define CAN_INIT_BRP_500k_16MHz     (UINT8)0x01    
#define CAN_INIT_TS_500k_16MHz      (UINT8)0x3A    

/*SJW Option*/
#define CAN_SJW01 2 /*SJW = SJW01 + 1 */

/*baud rate Option*/
#define CAN_INIT_BRP                CAN_INIT_BRP_500k_16MHz | (CAN_SJW01<<6) 
#define CAN_INIT_TS                 CAN_INIT_TS_500k_16MHz   
                                                    

/* set can accept hardware filters */
/* CANIDAR0xx:
** MSCAN Identifier Acceptance Registers
*/
/* CANIDMRxx:
** MSCAN Identifier Mask Registers
** Mask Bits:
** 1: Match corresponding acceptance code register and identifier bits
** 0: Ignore corresponding acceptance code register bit
** Note: These are different with Fresscale's datasheet
*/
//#define CAN_FILTER1_VAL 0x7FA
//#define CAN_FILTER1_MSK 0x7FA
#define CAN_FILTER1_VAL 0x704
#define CAN_FILTER1_MSK 0x704


#define CAN_FILTER2_VAL 0x7df
#define CAN_FILTER2_MSK 0x7df

#define CAN_FILTER3_VAL 0x760
#define CAN_FILTER3_MSK 0x760

//#define CAN_FILTER4_VAL 0x7FA
//#define CAN_FILTER4_MSK 0x7FA
#define CAN_FILTER4_VAL 0x704
#define CAN_FILTER4_MSK 0x704


/* software filter
 *  TRUE:   enable filter
 *  FALSE:  disable filter  
*/
#define CAN_RX_FILTER_SW        FALSE


/*
 * just for CAN GW.
 * Other module,please keep the default form (CAN_RX_FAST is FALSE)
*/
#define CAN_RX_FAST             FALSE


/* #define */
#define CAN_RX_BUFFER_SIZE          (30U)
#define CAN_TX_BUFFER_SIZE          (10U)


extern const CAN_FRAME_TYPE_E c_e_drvCanTypeCfg;
extern const BOOL c_b_drvCanWakeUpByBusCfg;
extern const BOOL c_b_drvCanBusoffRecoveryByUserCfg;
extern const BOOL c_b_drvCanSendFrameToBuf;
extern const BOOL c_b_drvCanSleepAfterInit;


#endif

/***********************end of drv_canCfg.h******************************************/

#if 0/*32bit filter*/

#define CAN_FILTER1_VAL 0x18FFA000
#define CAN_FILTER1_MSK 0x18FFA000
        
#define CAN_FILTER2_VAL 0x18FFA01D
#define CAN_FILTER2_MSK 0x18FFA01D

CANIDAR0 = (UINT8)((CAN_FILTER1_VAL>>21) & 0xFF);   /* Filter: [ID28: DI21]*/     
CANIDAR1 = (UINT8)((CAN_FILTER1_VAL>>15) & 0x07)|0x18|(UINT8)((CAN_FILTER1_VAL>>13) & 0xe0);/* Filter: [ID20:DI18] [SRR IDE] [ID17:ID15] */         
CANIDAR2 = (UINT8)((CAN_FILTER1_VAL>>7) & 0xFF);    /* Filter: [ID14: DI7]*/  
CANIDAR3 = (UINT8)((CAN_FILTER1_VAL<<1) & 0xFE);    /* Filter: [ID6 : DI0]; RTR=0*/  

CANIDMR0 = (UINT8)(~(UINT8)((CAN_FILTER1_MSK>>21) & 0xFF));   /* Filter: [ID28: DI21]*/     
CANIDMR1 = (UINT8)(~(UINT8)((CAN_FILTER1_MSK>>15) & 0x07)|0x18|(UINT8)((CAN_FILTER1_MSK>>13) & 0xe0));/* Filter: [ID20:DI18] [SRR IDE] [ID17:ID15] */   
CANIDMR2 = (UINT8)(~(UINT8)((CAN_FILTER1_MSK>>7) & 0xFF));    /* Filter: [ID14: DI7]*/  
CANIDMR3 = (UINT8)(~(UINT8)((CAN_FILTER1_MSK<<1) & 0xFE));    /* Filter: [ID6 : DI0]; RTR=0*/  


CANIDAR4 = (UINT8)((CAN_FILTER2_VAL>>21) & 0xFF);   /* Filter: [ID28: DI21]*/     
CANIDAR5 = (UINT8)((CAN_FILTER2_VAL>>15) & 0x07)|0x18|(UINT8)((CAN_FILTER2_VAL>>13) & 0xe0);/* Filter: [ID20:DI18] [SRR IDE] [ID17:ID15] */         
CANIDAR6 = (UINT8)((CAN_FILTER2_VAL>>7) & 0xFF);    /* Filter: [ID14: DI7]*/  
CANIDAR7 = (UINT8)((CAN_FILTER2_VAL<<1) & 0xFE);    /* Filter: [ID6 : DI0]; RTR=0*/  

CANIDMR4 = (UINT8)(~(UINT8)((CAN_FILTER2_MSK>>21) & 0xFF));   /* Filter: [ID28: DI21]*/     
CANIDMR5 = (UINT8)(~(UINT8)((CAN_FILTER2_MSK>>15) & 0x07)|0x18|(UINT8)((CAN_FILTER2_MSK>>13) & 0xe0));/* Filter: [ID20:DI18] [SRR IDE] [ID17:ID15] */   
CANIDMR6 = (UINT8)(~(UINT8)((CAN_FILTER2_MSK>>7) & 0xFF));    /* Filter: [ID14: DI7]*/  
CANIDMR7 = (UINT8)(~(UINT8)((CAN_FILTER2_MSK<<1) & 0xFE));    /* Filter: [ID6 : DI0]; RTR=0*/ 


#endif
/******************************************************************************
 Revision Notes:

For each change to this file, be sure to record:
1. Who made the change and when the change was made.
2. Why the change was made and the intended result.

  Date     By     Reason For Change
mm/dd/yy  XXX     -----------------

******************************************************************************/



